(Solved by Expert Tutors) ESE 330 Cadence Project 3 The following problem has to be done in Caden

Decoder Design in Static Combinational CMOS Logic

In this part you have to design 8-bit row decoder that converts 8 address bits into 256 wordlines with minimum possible delay using the logic effort. The maximum allowed capacitance on any address input is limited to 20 fF. The load capacitance at the word line is C_wordline?= 10 pF. You can implement the decoder with either 4 or 6 stages, as shown in Figure 1 and Figure 2. Using logic effort, calculate which implementation will give you the minimum delay. Use the implementation with smaller delay and size the logic gates for the optimal delay. Simulate the circuit in Cadence and report the minimum obtained delay.In calculations, assume that the capacitance Cg = 1.8 fF/?m

Decoder Design in Dynamic Domino Logic

Design the same function using the dynamic domino logic. Size the logic gates for the optimal delay from the rising edge of the clock using logic effort method and simulate the designed decoder in Cadence. How the delay compares to the delay obtained using static CMOS implementation?

 

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